`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2022/07/09 11:14:34
// Design Name: 
// Module Name: reg_EX
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////

module reg_EX(
    input clk,
    input rst_n,
    input wire [31:0] alu_c,
    input wire [31:0] pc,
    input wire [31:0] rd2,
    input wire [4:0] rd,
    input wire MemRW,
    input wire RegWEn,
    output reg RegWEn_out,
    input wire [1:0] WBSel,
    output reg [31:0] alu_c_out,
    output reg [31:0] pc_out,
    output reg [31:0] rd2_out,
    output reg [4:0] rd_out,
    output reg MemRW_out,
    output reg [1:0] WBSel_out
    );
    
always @(posedge clk or negedge rst_n) begin
    if(~rst_n) pc_out <= 32'h0000_0000;
    else       pc_out <= pc;
end

always @(posedge clk or negedge rst_n) begin
    if(~rst_n) rd2_out <= 32'h0000_0000;
    else       rd2_out <= rd2;
end    
    
always @(posedge clk or negedge rst_n) begin
    if(~rst_n) rd_out <= 5'b00000;
    else       rd_out <= rd;
end    
    
always @(posedge clk or negedge rst_n) begin
    if(~rst_n) WBSel_out <= 2'b00;
    else       WBSel_out <= WBSel;
end

always @(posedge clk or negedge rst_n) begin
    if(~rst_n) MemRW_out <= 0;
    else       MemRW_out <= MemRW;
end
  
always @(posedge clk or negedge rst_n) begin
    if(~rst_n) alu_c_out <= 0;
    else       alu_c_out <= alu_c;
end
 
 always @(posedge clk or negedge rst_n) begin
    if(~rst_n) RegWEn_out <= 0;
    else       RegWEn_out <= RegWEn;
end
 
endmodule
